diff --git a/docs/doc_sources/api_reference/dpctl/index.rst b/docs/doc_sources/api_reference/dpctl/index.rst
index 87fdfb16b2..6af99e288f 100644
--- a/docs/doc_sources/api_reference/dpctl/index.rst
+++ b/docs/doc_sources/api_reference/dpctl/index.rst
@@ -96,4 +96,5 @@
 .. toctree::
     :hidden:
 
+    constants
     filter_selector_string
diff --git a/docs/doc_sources/api_reference/dpctl/utils.rst b/docs/doc_sources/api_reference/dpctl/utils.rst
index b9fdad5051..093f298ff6 100644
--- a/docs/doc_sources/api_reference/dpctl/utils.rst
+++ b/docs/doc_sources/api_reference/dpctl/utils.rst
@@ -7,14 +7,11 @@
 
 .. currentmodule:: dpctl.utils
 
-.. autofunction:: get_execution_queue
-
-.. autofunction:: get_coerced_usm_type
-
-.. autofunction:: validate_usm_type
-
 .. autofunction:: onetrace_enabled
 
 .. autofunction:: intel_device_info
 
-.. autoexception:: ExecutionPlacementError
+.. data:: SequentialOrderManager
+
+    Thread-local object mapping each :class:`dpctl.SyclQueue` to an order
+    manager, used to ensure sequential ordering of offloaded tasks.
diff --git a/docs/doc_sources/api_reference/dpctl_capi.rst b/docs/doc_sources/api_reference/dpctl_capi.rst
index ce4b435aa6..db1e8257f2 100644
--- a/docs/doc_sources/api_reference/dpctl_capi.rst
+++ b/docs/doc_sources/api_reference/dpctl_capi.rst
@@ -177,7 +177,7 @@ API for :c:struct:`PySyclKernelObject`
 
 
 API for :c:struct:`PySyclKernelBundleObject`
----------------------------------------
+--------------------------------------------
 
 .. c:function:: DPCTLSyclKernelBundleRef SyclKernelBundle_GetKernelBundleRef(struct PySyclKernelBundleObject *prog)
 
diff --git a/docs/doc_sources/beginners_guides/installation.rst b/docs/doc_sources/beginners_guides/installation.rst
index c3d41bf658..edfa1b4dae 100644
--- a/docs/doc_sources/beginners_guides/installation.rst
+++ b/docs/doc_sources/beginners_guides/installation.rst
@@ -217,6 +217,7 @@ one architecture can be specified at a time.
 To determine the architecture code (``<arch>``) for your AMD GPU, run:
 
 .. code-block:: bash
+
     rocminfo | grep 'Name: *gfx.*'
 
 This will print names like ``gfx90a``, ``gfx1030``, etc.
@@ -225,6 +226,7 @@ You can then use one of them as the argument to ``--target-hip``.
 For example:
 
 .. code-block:: bash
+
     python scripts/build_locally.py --verbose --target-hip=gfx1030
 
 Alternatively, you can use the ``DPCTL_TARGET_HIP`` CMake option:
diff --git a/docs/doc_sources/user_guides/environment_variables.rst b/docs/doc_sources/user_guides/environment_variables.rst
index db697127bb..77386ac388 100644
--- a/docs/doc_sources/user_guides/environment_variables.rst
+++ b/docs/doc_sources/user_guides/environment_variables.rst
@@ -42,7 +42,7 @@ The value of the variable is a bit-mask, with the following supported values:
 .. _env_var_ze_flat_device_hierarchy:
 
 Variable ``ZE_FLAT_DEVICE_HIERARCHY``
---------------------------
+-------------------------------------
 Allows users to define the device hierarchy model exposed by Level Zero driver implementation.
 Keep in mind :py:mod:`dpctl.get_composite_devices` will only work while this is set to ``COMBINED``.
 
@@ -58,7 +58,7 @@ Keep in mind :py:mod:`dpctl.get_composite_devices` will only work while this is
     * - ``FLAT``
       - Level Zero devices with multiple tiles will be exposed as a set of root devices, each corresponding to an individual tile. Enabled by default.
 
-Read more about device hierarchy in `Level Zero Specification <https://oneapi-src.github.io/level-zero-spec/level-zero/latest/core/PROG.html#device-hierarchy>`_ and `Intel GPU article <https://www.intel.com/content/www/us/en/developer/articles/technical/flattening-gpu-tile-hierarchy.html>`_.
+Read more about device hierarchy in `Level Zero Specification <https://oneapi-src.github.io/level-zero-spec/level-zero/latest/core/PROG.html#device-hierarchy>`__ and `Intel GPU article <https://www.intel.com/content/www/us/en/developer/articles/technical/flattening-gpu-tile-hierarchy.html>`__.
 
 Variable ``ZE_AFFINITY_MASK``
 -------------------------------
@@ -76,10 +76,10 @@ Therefore, we could use the second tile in each of four dual-tile GPUs with ``ZE
 | **If the exposed tiles belong to different physical devices:**
 | - A composite device is available for each physical device, and the tiles are accessible as component devices of their respective composite device.
 
-Additional examples to illustrate this are in the detailed documentation for ``ZE_AFFINITY_MASK``, read more about it in `Level Zero Specification <https://oneapi-src.github.io/level-zero-spec/level-zero/latest/core/PROG.html#affinity-mask>`_.
+Additional examples to illustrate this are in the detailed documentation for ``ZE_AFFINITY_MASK``, read more about it in `Level Zero Specification <https://oneapi-src.github.io/level-zero-spec/level-zero/latest/core/PROG.html#affinity-mask>`__.
 
 Variable ``ZE_ENABLE_PCI_ID_DEVICE_ORDER``
--------------------------------
+------------------------------------------
 Forces driver to report devices from lowest to highest PCI bus ID.
 
 .. list-table::
@@ -93,7 +93,7 @@ Forces driver to report devices from lowest to highest PCI bus ID.
       - Enabled.
 
 Variable ``ZE_SHARED_FORCE_DEVICE_ALLOC``
--------------------------------
+-----------------------------------------
 Forces all shared allocations into device memory
 
 .. list-table::